1. Field of the Invention
Example embodiments of the present invention relate generally to a voltage generator and methods thereof, and more particularly to a voltage generator generating voltages associated with a read operation and methods thereof.
2. Description of the Related Art
Data may be stored in each of a plurality of memory cells of a flash memory as a first logic level (e.g., a higher logic level or logic “1”) or a second logic level (e.g., a lower logic level or logic “0”). In order to read data from a memory cell of a flash memory, a read command for the memory cell may be enabled, and a given voltage may be applied to the memory cell. The applied voltage may not be a voltage provided by a pad of the flash memory, but rather may typically be generated inside the flash memory based on electrical characteristics of the memory cell.
The voltage applied to the memory cell to read data from the memory cell may be generated by a voltage generator inside a flash memory. In order to reduce power consumption of the flash memory, the voltage generator may be driven (e.g., operated) only during read operations of the flash memory. Therefore, the speed of reading data from the flash memory may be at least partially dependent on how quickly the voltage generator can generate a voltage to be applied to the flash memory.
FIG. 1 is a circuit diagram of a conventional voltage generator 100. Referring to FIG. 1, the voltage generator 100 may include a voltage comparison block 110 and a voltage generation block 120. The voltage generator 100 may generate a comparison voltage Vrd in response to a read command READ and a reference voltage Vref.
Referring to FIG. 1, the voltage comparison block 110 may generate an output voltage VO in response to the read command READ. The output voltage VO may correspond to a difference between the reference voltage Vref and a determination voltage Vdet. The voltage generation block 120 may output the determination voltage Vdet and the comparison voltage Vrd in response to the read command READ, an inverse read command READB whose phase may be opposite to the phase of the read command READ, and the output voltage VO. The comparison voltage Vrd may be used to read data from a flash memory cell.
Conventional operation of the voltage generator 100 will now be described. Below, nodes and voltages output from the respective nodes will now be referenced by the same reference characters. Hereinafter, a comparison voltage and a node from which the comparison voltage may be output are both referenced by reference character Vrd. Conventional operation will be described wherein the read command READ is enabled (e.g., set to a first logic level, such as a higher logic level or logic “1”) and disabled (e.g., set to a second logic level, such as a lower logic level or logic “0”).
In conventional operation of the voltage generator 100, if the read command READ is disabled (e.g., set to the second logic level), a third N-type MOS transistor N3 may be turned off, and thus, the voltage comparison block 110 may not operate. A fifth P-type MOS transistor P5 may be turned off, and a fourth P-type MOS transistor P4 may be turned on. Thus, the comparison voltage Vrd may be fixed to a voltage level substantially the same as a first power supply voltage VCC. Thus, if the read command READ is disabled, the voltage comparison block 110 and the voltage generation block 120 may consume a relatively small amount of power.
In conventional operation of the voltage generator 100, if the read command READ is enabled (e.g., set to the first logic level), the third N-type MOS transistor N3 and the fifth P-type MOS transistor P5 may be turned on, and the fourth P-type MOS transistor P4 may be turned off. Accordingly, the voltage comparison block 110 and the voltage generation block 120 may operate normally.
As discussed above, if the read command READ is disabled, the comparison voltage output node Vrd may be precharged to approximately the same voltage level as the first power supply voltage VCC. However, if the read command READ is enabled, the determination voltage Vdet may be determined. The determination voltage Vdet and the reference voltage Vref may be compared with each other by the voltage comparison block 110, and the output voltage VO, which may be generated as a result of the comparison, may be fed back to the voltage generation block 120. A current supplied by the first power supply voltage VCC may be adjusted by the output voltage VO controlling the third P-type MOS transistor P3. Then, the determination voltage Vdet, which may be applied to a resistor R2, may be adjusted. The determination voltage Vdet may be applied to the voltage comparison block 110.
The above-described voltage adjustment operation may be performed repeatedly until the determination voltage Vdet substantially matches the reference voltage Vref. After a given number of repetitions, the comparison voltage Vrd may approximate a given voltage level. The comparison voltage Vrd may be expressed as follows,
                              V          rd                =                              V            det                    ×                      (                          1              +                                                R                  ⁢                                                                          ⁢                  1                                                  R                  ⁢                                                                          ⁢                  2                                                      )                                              Equation        ⁢                                  ⁢        1            
Generally, the faster the comparison voltage Vrd is generated after the read command READ is enabled, the more efficient the voltage generator 100. In a semiconductor layout, resistors may be embodied as a plurality of unit rectangles which have a substantially uniform resistance and may be connected in series. Generally, the greater the number of unit rectangles connected in series, the greater the resistance, and the longer the path along which electric charges may be transmitted. Thus, because higher resistance is associated with a longer propagation path, as the resistance of first and second resistors R1 and R2 increases, the speed of generating the comparison voltage Vrd may decrease. However, if the resistance of the first and second resistors R1 and R2 is reduced to generate the comparison voltage Vrd within a shorter period of time, an amount of direct current transmitted from the first power supply voltage VCC to a second power supply voltage VSS may increase, and thus, the power consumption of the voltage generator 100 may increase. Therefore, it may be difficult to reduce the resistance of the resistors R1 and R2 to generate the comparison voltage Vrd more quickly because reducing the resistance may cause an increase to the power consumption of the voltage generator 100.